SPARC Enterprise T1000 POST log


aressc> setsc diag_level max
aressc> setsc diag_verbosity max
aressc> setsc diag_trigger user-reset
aressc> console -f
Warning: User < > currently has write permission to this console and forcibly removing them will terminate any current write actions and all work will be lost.  Would you like to continue? [y/n]y
Enter #. to return to ALOM.

{0} ok reset-all
SC Alert: Host System has Reset

2012-07-23 17:53:02.843 0:0:0>
2012-07-23 17:53:02.885 0:0:0>SPARC-Enterprise[TM] T1000 POST 4.30.4.b 2010/07/09 14:25 
       /export/delivery/delivery/4.30/4.30.4.b/post4.30.4-micro/Niagara/erie/integrated  (root)  
2012-07-23 17:53:03.111 0:0:0>Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
2012-07-23 17:53:03.257 0:0:0>VBSC cmp0 arg is: 00ffffff.00000311
2012-07-23 17:53:03.345 0:0:0>POST enabling threads: 00000000.00ffffff
2012-07-23 17:53:03.441 0:0:0>VBSC cntl arg is: 00ffffff.00000311
2012-07-23 17:53:03.529 0:0:0>VBSC selecting POST MAX Testing.
2012-07-23 17:53:03.616 0:0:0>VBSC setting verbosity level 3
2012-07-23 17:53:03.706 0:0:0>  Niagara, Version 2.0
2012-07-23 17:53:03.790 0:0:0>  Serial Number = %%%%%%%%.%%%%%%%%
2012-07-23 17:53:04.254 0:0:0>Start Selftest.....
2012-07-23 17:53:04.660 0:0:0>Begin: Init CPU
2012-07-23 17:53:04.869 0:0:0>End  : Init CPU
2012-07-23 17:53:04.936 0:0:0>Master CPU Tests Basic.....
2012-07-23 17:53:05.051 0:0:0>CPU =: 0
2012-07-23 17:53:05.149 0:0:0>Begin: DMMU Registers Access
2012-07-23 17:53:05.398 0:0:0>End  : DMMU Registers Access
2012-07-23 17:53:05.491 0:0:0>Begin: IMMU Registers Access
2012-07-23 17:53:05.707 0:0:0>End  : IMMU Registers Access
2012-07-23 17:53:05.800 0:0:0>Begin: Common MMU regs
2012-07-23 17:53:06.057 0:0:0>End  : Common MMU regs
2012-07-23 17:53:06.179 0:0:0>Begin: D-Cache RAM
2012-07-23 17:53:07.505 0:0:0>End  : D-Cache RAM
2012-07-23 17:53:07.588 0:0:0>Init MMU.....
2012-07-23 17:53:10.122 0:0:0>Begin: Setup DMMU Miss Handler
2012-07-23 17:53:10.226 0:0:0>End  : Setup DMMU Miss Handler
2012-07-23 17:53:10.324 0:0:0>Begin: Init JBUS Config Regs
2012-07-23 17:53:10.427 0:0:0>End  : Init JBUS Config Regs
2012-07-23 17:53:10.552 0:0:0>Begin: IO-Bridge unit 1 init test             
2012-07-23 17:53:12.650 0:0:0>End  : IO-Bridge unit 1 init test             
2012-07-23 17:53:13.768 0:0:0>Sys 200 MHz, CPU 1000 MHz, Mem 200 MHz 
2012-07-23 17:53:13.883 0:0:0>Begin: Integrated POST Testing
2012-07-23 17:53:13.989 0:0:0>End  : Integrated POST Testing
2012-07-23 17:53:14.081 0:0:0>L2 Tests.....
2012-07-23 17:53:14.165 0:0:0>Begin: Setup L2 Cache
2012-07-23 17:53:14.256 0:0:0>L2 Cache Control = 00000000.00300000 
2012-07-23 17:53:14.360 0:0:0>End  : Setup L2 Cache
2012-07-23 17:53:14.452 0:0:0>Begin: L2 Cache UA Array Test
2012-07-23 17:53:15.129 0:0:0>End  : L2 Cache UA Array Test
2012-07-23 17:53:15.220 0:0:0>Begin: L2 Cache VD Array Test
2012-07-23 17:53:15.893 0:0:0>End  : L2 Cache VD Array Test
2012-07-23 17:53:15.986 0:0:0>Begin: L2 Cache Tags Test
2012-07-23 17:53:23.098 0:0:0>End  : L2 Cache Tags Test
2012-07-23 17:53:23.190 0:0:0>Begin: Scrub and Setup L2 Cache
2012-07-23 17:53:23.284 0:0:0>L2 Directory clear
2012-07-23 17:53:23.360 0:0:0>L2 Scrub VD & UA
2012-07-23 17:53:23.563 0:0:0>L2 Scrub Tags
2012-07-23 17:53:24.962 0:0:0>End  : Scrub and Setup L2 Cache
2012-07-23 17:53:25.053 0:0:0>Test Memory.....
2012-07-23 17:53:25.140 0:0:0>Begin: Probe and Setup Memory
2012-07-23 17:53:25.231 0:0:0>INFO:       4096MB at Memory Channel [0 3 ] Rank 0 Stack 0
2012-07-23 17:53:25.375 0:0:0>INFO:          0MB at Memory Channel [0 3 ] Rank 0 Stack 1
2012-07-23 17:53:25.589 0:0:0>INFO:       4096MB at Memory Channel [0 3 ] Rank 1 Stack 0
2012-07-23 17:53:25.733 0:0:0>INFO:          0MB at Memory Channel [0 3 ] Rank 1 Stack 1
2012-07-23 17:53:25.877 0:0:0>
2012-07-23 17:53:25.931 0:0:0>End  : Probe and Setup Memory
2012-07-23 17:53:26.025 0:0:0>Begin: Data Bitwalk
2012-07-23 17:53:26.103 0:0:0>L2 Scrub Data
2012-07-23 17:53:53.466 0:0:0>L2 Enable
2012-07-23 17:53:53.525 0:0:0>  Testing Memory Channel 0 Rank 0 Stack 0 
2012-07-23 17:53:55.761 0:0:0>  Testing Memory Channel 3 Rank 0 Stack 0 
2012-07-23 17:53:57.998 0:0:0>  Testing Memory Channel 0 Rank 1 Stack 0 
2012-07-23 17:54:00.235 0:0:0>  Testing Memory Channel 3 Rank 1 Stack 0 
2012-07-23 17:54:02.468 0:0:0>L2 Directory clear
2012-07-23 17:54:02.544 0:0:0>L2 Scrub VD & UA
2012-07-23 17:54:02.745 0:0:0>L2 Scrub Tags
2012-07-23 17:54:04.129 0:0:0>L2 Disable 
2012-07-23 17:54:04.192 0:0:0>End  : Data Bitwalk
2012-07-23 17:54:04.279 0:0:0>Begin: Address Bitwalk
2012-07-23 17:54:04.366 0:0:0>  Testing Memory Channel 0 Rank 0 Stack 0 
2012-07-23 17:54:04.926 0:0:0>  Testing Memory Channel 3 Rank 0 Stack 0 
2012-07-23 17:54:05.482 0:0:0>  Testing Memory Channel 0 Rank 1 Stack 0 
2012-07-23 17:54:06.026 0:0:0>  Testing Memory Channel 3 Rank 1 Stack 0 
2012-07-23 17:54:06.577 0:0:0>End  : Address Bitwalk
2012-07-23 17:54:06.669 0:0:0>Setup POST Mailbox .....
2012-07-23 17:54:06.776 0:0:0>Begin: Test Mailbox region
2012-07-23 17:54:06.862 0:0:0>..
2012-07-23 17:54:20.891 0:0:0>End  : Test Mailbox region
2012-07-23 17:54:20.983 0:0:0>Begin: Set Mailbox
2012-07-23 17:54:22.480 0:0:0>Begin: Setup Final DMMU Entries
2012-07-23 17:54:22.588 0:0:0>End  : Setup Final DMMU Entries
2012-07-23 17:54:22.701 0:0:0>Begin: Post Image Region Scrub
2012-07-23 17:54:23.175 0:0:0>End  : Post Image Region Scrub
2012-07-23 17:54:23.280 0:0:0>Begin: Run POST from Memory
2012-07-23 17:54:33.723 0:0:0>Verifying checksum on copied image.
2012-07-23 17:54:33.810 0:0:0>The Memory's CHECKSUM value is 2968.
2012-07-23 17:54:33.898 0:0:0>The Memory's Content Size value is 8c752.
2012-07-23 17:54:41.760 0:0:0>Success...  Checksum on Memory Validated.
2012-07-23 17:54:41.861 0:0:0>End  : Run POST from Memory
2012-07-23 17:54:41.947 0:0:0>Begin: L2 Cache Ram Test
2012-07-23 17:54:45.482 0:0:0>End  : L2 Cache Ram Test
2012-07-23 17:54:45.505 0:0:0>Begin: Enable L2 Cache
2012-07-23 17:54:45.522 0:0:0>L2 Scrub Data
2012-07-23 17:54:46.323 0:0:0>L2 Enable
2012-07-23 17:54:46.331 0:0:0>End  : Enable L2 Cache
2012-07-23 17:54:47.304 0:0:0>CPU =: 0 4 8 12 16 20
2012-07-23 17:54:47.495 0:1:0>Begin: DMMU Registers Access
2012-07-23 17:54:47.513 0:2:0>Begin: DMMU Registers Access
2012-07-23 17:54:47.533 0:3:0>Begin: DMMU Registers Access
2012-07-23 17:54:47.549 0:4:0>Begin: DMMU Registers Access
2012-07-23 17:54:47.568 0:5:0>Begin: DMMU Registers Access
2012-07-23 17:54:47.589 0:1:0>End  : DMMU Registers Access
2012-07-23 17:54:47.614 0:2:0>End  : DMMU Registers Access
2012-07-23 17:54:47.636 0:3:0>End  : DMMU Registers Access
2012-07-23 17:54:47.652 0:4:0>End  : DMMU Registers Access
2012-07-23 17:54:47.669 0:5:0>End  : DMMU Registers Access
2012-07-23 17:54:47.693 0:1:0>Begin: IMMU Registers Access
2012-07-23 17:54:47.716 0:2:0>Begin: IMMU Registers Access
2012-07-23 17:54:47.740 0:3:0>Begin: IMMU Registers Access
2012-07-23 17:54:47.763 0:4:0>Begin: IMMU Registers Access
2012-07-23 17:54:47.794 0:5:0>Begin: IMMU Registers Access
2012-07-23 17:54:47.810 0:1:0>End  : IMMU Registers Access
2012-07-23 17:54:47.827 0:2:0>End  : IMMU Registers Access
2012-07-23 17:54:47.858 0:3:0>End  : IMMU Registers Access
2012-07-23 17:54:47.876 0:4:0>End  : IMMU Registers Access
2012-07-23 17:54:47.900 0:5:0>End  : IMMU Registers Access
2012-07-23 17:54:47.916 0:1:0>Begin: Common MMU regs
2012-07-23 17:54:47.937 0:2:0>Begin: Common MMU regs
2012-07-23 17:54:47.958 0:3:0>Begin: Common MMU regs
2012-07-23 17:54:47.982 0:4:0>Begin: Common MMU regs
2012-07-23 17:54:48.010 0:5:0>Begin: Common MMU regs
2012-07-23 17:54:48.042 0:1:0>End  : Common MMU regs
2012-07-23 17:54:48.076 0:2:0>End  : Common MMU regs
2012-07-23 17:54:48.117 0:3:0>End  : Common MMU regs
2012-07-23 17:54:48.139 0:4:0>End  : Common MMU regs
2012-07-23 17:54:48.159 0:5:0>End  : Common MMU regs
2012-07-23 17:54:48.184 0:1:0>Begin: D-Cache RAM
2012-07-23 17:54:48.215 0:1:0>End  : D-Cache RAM
2012-07-23 17:54:48.235 0:2:0>Begin: D-Cache RAM
2012-07-23 17:54:48.257 0:3:0>Begin: D-Cache RAM
2012-07-23 17:54:48.279 0:4:0>Begin: D-Cache RAM
2012-07-23 17:54:48.300 0:5:0>Begin: D-Cache RAM
2012-07-23 17:54:48.321 0:2:0>End  : D-Cache RAM
2012-07-23 17:54:48.343 0:3:0>End  : D-Cache RAM
2012-07-23 17:54:48.365 0:4:0>End  : D-Cache RAM
2012-07-23 17:54:48.387 0:5:0>End  : D-Cache RAM
2012-07-23 17:54:48.665 0:1:0>Begin: Setup DMMU Miss Handler
2012-07-23 17:54:48.686 0:2:0>Begin: Setup DMMU Miss Handler
2012-07-23 17:54:48.702 0:3:0>Begin: Setup DMMU Miss Handler
2012-07-23 17:54:48.724 0:4:0>Begin: Setup DMMU Miss Handler
2012-07-23 17:54:48.745 0:5:0>Begin: Setup DMMU Miss Handler
2012-07-23 17:54:48.769 0:1:0>End  : Setup DMMU Miss Handler
2012-07-23 17:54:48.791 0:2:0>End  : Setup DMMU Miss Handler
2012-07-23 17:54:48.813 0:3:0>End  : Setup DMMU Miss Handler
2012-07-23 17:54:48.832 0:4:0>End  : Setup DMMU Miss Handler
2012-07-23 17:54:48.863 0:5:0>End  : Setup DMMU Miss Handler
2012-07-23 17:54:52.226 0:0:0>CPU =: 0-23
2012-07-23 17:54:52.268 0:0:0>Test slave strand registers...
2012-07-23 17:54:53.431 0:1:0>Begin: D-Cache Tags
2012-07-23 17:54:53.455 0:2:0>Begin: D-Cache Tags
2012-07-23 17:54:53.477 0:3:0>Begin: D-Cache Tags
2012-07-23 17:54:53.499 0:4:0>Begin: D-Cache Tags
2012-07-23 17:54:53.522 0:5:0>Begin: D-Cache Tags
2012-07-23 17:54:53.544 0:0:0>Extended CPU Tests.....
2012-07-23 17:54:53.575 0:1:0>End  : D-Cache Tags
2012-07-23 17:54:53.604 0:2:0>End  : D-Cache Tags
2012-07-23 17:54:53.628 0:3:0>End  : D-Cache Tags
2012-07-23 17:54:53.651 0:4:0>End  : D-Cache Tags
2012-07-23 17:54:53.675 0:5:0>End  : D-Cache Tags
2012-07-23 17:54:53.696 0:0:0>Begin: D-Cache Tags
2012-07-23 17:54:53.718 0:1:0>Begin: I-Cache RAM Test
2012-07-23 17:54:53.741 0:2:0>Begin: I-Cache RAM Test
2012-07-23 17:54:53.765 0:3:0>Begin: I-Cache RAM Test
2012-07-23 17:54:53.801 0:4:0>Begin: I-Cache RAM Test
2012-07-23 17:54:53.824 0:5:0>Begin: I-Cache RAM Test
2012-07-23 17:54:53.845 0:0:0>End  : D-Cache Tags
2012-07-23 17:54:53.860 0:1:0>End  : I-Cache RAM Test
2012-07-23 17:54:53.875 0:2:0>End  : I-Cache RAM Test
2012-07-23 17:54:53.898 0:3:0>End  : I-Cache RAM Test
2012-07-23 17:54:53.921 0:4:0>End  : I-Cache RAM Test
2012-07-23 17:54:53.943 0:5:0>End  : I-Cache RAM Test
2012-07-23 17:54:53.964 0:0:0>Begin: I-Cache RAM Test
2012-07-23 17:54:53.984 0:1:0>Begin: I-Cache Tag RAM
2012-07-23 17:54:54.002 0:2:0>Begin: I-Cache Tag RAM
2012-07-23 17:54:54.027 0:3:0>Begin: I-Cache Tag RAM
2012-07-23 17:54:54.059 0:4:0>Begin: I-Cache Tag RAM
2012-07-23 17:54:54.079 0:5:0>Begin: I-Cache Tag RAM
2012-07-23 17:54:54.098 0:0:0>End  : I-Cache RAM Test
2012-07-23 17:54:54.120 0:1:0>End  : I-Cache Tag RAM
2012-07-23 17:54:54.159 0:2:0>End  : I-Cache Tag RAM
2012-07-23 17:54:54.197 0:3:0>End  : I-Cache Tag RAM
2012-07-23 17:54:54.234 0:4:0>End  : I-Cache Tag RAM
2012-07-23 17:54:54.273 0:5:0>End  : I-Cache Tag RAM
2012-07-23 17:54:54.314 0:0:0>Begin: I-Cache Tag RAM
2012-07-23 17:54:54.361 0:0:0>End  : I-Cache Tag RAM
2012-07-23 17:54:54.419 0:5:0>Begin: FPU Registers and Data Path
2012-07-23 17:54:54.468 0:1:0>Begin: FPU Registers and Data Path
2012-07-23 17:54:54.526 0:2:0>Begin: FPU Registers and Data Path
2012-07-23 17:54:54.570 0:3:0>Begin: FPU Registers and Data Path
2012-07-23 17:54:54.618 0:4:0>Begin: FPU Registers and Data Path
2012-07-23 17:54:54.663 0:5:0>End  : FPU Registers and Data Path
2012-07-23 17:54:54.717 0:0:0>Begin: FPU Registers and Data Path
2012-07-23 17:54:54.787 0:1:0>End  : FPU Registers and Data Path
2012-07-23 17:54:54.871 0:2:0>End  : FPU Registers and Data Path
2012-07-23 17:54:54.944 0:3:0>End  : FPU Registers and Data Path
2012-07-23 17:54:55.017 0:4:0>End  : FPU Registers and Data Path
2012-07-23 17:54:55.077 0:5:0>Begin: FPU Move Registers
2012-07-23 17:54:55.129 0:0:0>End  : FPU Registers and Data Path
2012-07-23 17:54:55.189 0:1:0>Begin: FPU Move Registers
2012-07-23 17:54:55.244 0:2:0>Begin: FPU Move Registers
2012-07-23 17:54:55.302 0:3:0>Begin: FPU Move Registers
2012-07-23 17:54:55.360 0:4:0>Begin: FPU Move Registers
2012-07-23 17:54:55.416 0:5:0>End  : FPU Move Registers
2012-07-23 17:54:55.469 0:0:0>Begin: FPU Move Registers
2012-07-23 17:54:55.528 0:1:0>End  : FPU Move Registers
2012-07-23 17:54:55.587 0:2:0>End  : FPU Move Registers
2012-07-23 17:54:55.646 0:3:0>End  : FPU Move Registers
2012-07-23 17:54:55.704 0:4:0>End  : FPU Move Registers
2012-07-23 17:54:55.761 0:5:0>Begin: FSR Read/Write
2012-07-23 17:54:55.816 0:0:0>End  : FPU Move Registers
2012-07-23 17:54:55.898 0:1:0>Begin: FSR Read/Write
2012-07-23 17:54:55.935 0:2:0>Begin: FSR Read/Write
2012-07-23 17:54:56.012 0:3:0>Begin: FSR Read/Write
2012-07-23 17:54:56.053 0:4:0>Begin: FSR Read/Write
2012-07-23 17:54:56.088 0:5:0>End  : FSR Read/Write
2012-07-23 17:54:56.124 0:0:0>Begin: FSR Read/Write
2012-07-23 17:54:56.161 0:1:0>End  : FSR Read/Write
2012-07-23 17:54:56.199 0:2:0>End  : FSR Read/Write
2012-07-23 17:54:56.234 0:3:0>End  : FSR Read/Write
2012-07-23 17:54:56.270 0:4:0>End  : FSR Read/Write
2012-07-23 17:54:56.305 0:5:0>Begin: FPU Branch Instructions
2012-07-23 17:54:56.345 0:0:0>End  : FSR Read/Write
2012-07-23 17:54:56.382 0:1:0>Begin: FPU Branch Instructions
2012-07-23 17:54:56.423 0:2:0>Begin: FPU Branch Instructions
2012-07-23 17:54:56.469 0:3:0>Begin: FPU Branch Instructions
2012-07-23 17:54:56.512 0:4:0>Begin: FPU Branch Instructions
2012-07-23 17:54:56.565 0:0:0>Begin: FPU Branch Instructions
2012-07-23 17:54:56.738 0:5:0>End  : FPU Branch Instructions
2012-07-23 17:54:56.786 0:1:0>End  : FPU Branch Instructions
2012-07-23 17:54:56.833 0:5:0>Begin: FPU Functional Test
2012-07-23 17:54:56.879 0:1:0>Begin: FPU Functional Test
2012-07-23 17:54:56.925 0:2:0>End  : FPU Branch Instructions
2012-07-23 17:54:56.970 0:3:0>End  : FPU Branch Instructions
2012-07-23 17:54:57.012 0:4:0>End  : FPU Branch Instructions
2012-07-23 17:54:57.052 0:0:0>End  : FPU Branch Instructions
2012-07-23 17:54:57.092 0:2:0>Begin: FPU Functional Test
2012-07-23 17:54:57.133 0:3:0>Begin: FPU Functional Test
2012-07-23 17:54:57.175 0:4:0>Begin: FPU Functional Test
2012-07-23 17:54:57.218 0:0:0>Begin: FPU Functional Test
2012-07-23 17:54:57.989 0:1:0>End  : FPU Functional Test
2012-07-23 17:54:58.068 0:0:0>End  : FPU Functional Test
2012-07-23 17:54:58.182 0:2:0>End  : FPU Functional Test
2012-07-23 17:54:58.206 0:3:0>End  : FPU Functional Test
2012-07-23 17:54:58.221 0:4:0>End  : FPU Functional Test
2012-07-23 17:54:58.243 0:5:0>End  : FPU Functional Test
2012-07-23 17:54:58.550 0:0:0>Scrub Memory.....
2012-07-23 17:54:58.571 0:0:0>Begin: Scrub Memory
2012-07-23 17:54:58.587 0:0:0>Scrub 00000000.00500000->00000001.00000000 on Memory Channel [0 3 ] Rank 0 Stack 0
2012-07-23 17:55:00.214 0:0:0>Scrub 00000001.00000000->00000002.00000000 on Memory Channel [0 3 ] Rank 1 Stack 0
2012-07-23 17:55:01.964 0:0:0>End  : Scrub Memory
2012-07-23 17:55:02.116 0:4:0>Begin: IMMU Functional
2012-07-23 17:55:02.138 0:5:0>Begin: IMMU Functional
2012-07-23 17:55:02.162 0:1:0>Begin: IMMU Functional
2012-07-23 17:55:02.197 0:2:0>Begin: IMMU Functional
2012-07-23 17:55:02.214 0:3:0>Begin: IMMU Functional
2012-07-23 17:55:02.236 0:4:0>End  : IMMU Functional
2012-07-23 17:55:02.266 0:5:0>End  : IMMU Functional
2012-07-23 17:55:02.286 0:0:0>Functional CPU Tests.....
2012-07-23 17:55:02.316 0:1:0>End  : IMMU Functional
2012-07-23 17:55:02.334 0:2:0>End  : IMMU Functional
2012-07-23 17:55:02.357 0:3:0>End  : IMMU Functional
2012-07-23 17:55:02.374 0:4:0>Begin: DMMU Functional
2012-07-23 17:55:02.396 0:5:0>Begin: DMMU Functional
2012-07-23 17:55:02.418 0:0:0>Begin: IMMU Functional
2012-07-23 17:55:02.439 0:1:0>Begin: DMMU Functional
2012-07-23 17:55:02.464 0:2:0>Begin: DMMU Functional
2012-07-23 17:55:02.485 0:3:0>Begin: DMMU Functional
2012-07-23 17:55:02.508 0:4:0>End  : DMMU Functional
2012-07-23 17:55:02.531 0:5:0>End  : DMMU Functional
2012-07-23 17:55:02.552 0:0:0>End  : IMMU Functional
2012-07-23 17:55:02.575 0:1:0>End  : DMMU Functional
2012-07-23 17:55:02.608 0:2:0>End  : DMMU Functional
2012-07-23 17:55:02.629 0:3:0>End  : DMMU Functional
2012-07-23 17:55:02.652 0:0:0>Begin: DMMU Functional
2012-07-23 17:55:02.691 0:0:0>End  : DMMU Functional
2012-07-23 17:55:02.713 0:0:0>Extended Memory Tests.....
2012-07-23 17:55:02.751 0:0:0>Begin: Print Mem Config
2012-07-23 17:55:02.779 0:0:0>Caches : Icache is ON, Dcache is ON.
2012-07-23 17:55:02.794 0:0:0>  Bank 0   4096MB : 00000000.00000000 -> 00000001.00000000.
2012-07-23 17:55:02.816 0:0:0>  Bank 2   4096MB : 00000001.00000000 -> 00000002.00000000.
2012-07-23 17:55:02.853 0:0:0>End  : Print Mem Config
2012-07-23 17:55:02.877 0:0:0>Begin: Block Mem Test
2012-07-23 17:55:02.900 0:0:0>Test 4289724416 bytes at 00000000.00500000 Memory Channel [ 0 3 ] Rank 0 Stack 0
2012-07-23 17:55:03.073 0:0:0>........
2012-07-23 17:55:31.102 0:0:0>Test 4294967296 bytes at 00000001.00000000 Memory Channel [ 0 3 ] Rank 1 Stack 0
2012-07-23 17:55:31.248 0:0:0>........
2012-07-23 17:55:59.066 0:0:0>End  : Block Mem Test
2012-07-23 17:55:59.095 0:0:0>IO-Bridge Tests.....
2012-07-23 17:55:59.118 0:0:0>Begin: IO-Bridge Quick Read             
2012-07-23 17:55:59.134 0:0:0>
2012-07-23 17:55:59.148 0:0:0>--------------------------------------------------------------
2012-07-23 17:55:59.185 0:0:0>--------- IO-Bridge Quick Read Only of CSR and ID ---------------
2012-07-23 17:55:59.203 0:0:0>--------------------------------------------------------------
2012-07-23 17:55:59.229 0:0:0>fire 1 JBUSID  00000080.0f000000 =           
2012-07-23 17:55:59.246 0:0:0>                                   fc000002.e03dda24
2012-07-23 17:55:59.268 0:0:0>--------------------------------------------------------------
2012-07-23 17:55:59.300 0:0:0>fire 1 JBUSCSR 00000080.0f410000 =           
2012-07-23 17:55:59.321 0:0:0>                                   00000ff5.13cb7000
2012-07-23 17:55:59.337 0:0:0>--------------------------------------------------------------
2012-07-23 17:55:59.357 0:0:0>End  : IO-Bridge Quick Read             
2012-07-23 17:55:59.382 0:0:0>Begin: IO-Bridge unit 1 jbus perf test        
2012-07-23 17:55:59.407 0:0:0>End  : IO-Bridge unit 1 jbus perf test        
2012-07-23 17:55:59.429 0:0:0>Begin: IO-Bridge unit 1 int init test 
2012-07-23 17:55:59.461 0:0:0>End  : IO-Bridge unit 1 int init test 
2012-07-23 17:55:59.482 0:0:0>Begin: IO-Bridge unit 1 msi init test 
2012-07-23 17:55:59.517 0:0:0>End  : IO-Bridge unit 1 msi init test 
2012-07-23 17:55:59.541 0:0:0>Begin: IO-Bridge unit 1 ilu init test 
2012-07-23 17:55:59.562 0:0:0>End  : IO-Bridge unit 1 ilu init test 
2012-07-23 17:55:59.582 0:0:0>Begin: IO-Bridge unit 1 tlu init test 
2012-07-23 17:55:59.610 0:0:0>End  : IO-Bridge unit 1 tlu init test 
2012-07-23 17:55:59.625 0:0:0>Begin: IO-Bridge unit 1 lpu init test 
2012-07-23 17:55:59.654 0:0:0>End  : IO-Bridge unit 1 lpu init test 
2012-07-23 17:55:59.689 0:0:0>Begin: IO-Bridge unit 1 link train port B   
2012-07-23 17:55:59.727 0:0:0>End  : IO-Bridge unit 1 link train port B   
2012-07-23 17:55:59.747 0:0:0>Begin: IO-Bridge unit 1 interrupt test   
2012-07-23 17:55:59.769 0:0:0>End  : IO-Bridge unit 1 interrupt test   
2012-07-23 17:55:59.793 0:0:0>Begin: IO-Bridge unit 1 Config MB bridges
2012-07-23 17:55:59.814 0:0:0>Config port B, bus 2 dev 0 func 0, tag 5714 BRIDGE
2012-07-23 17:55:59.836 0:0:0>Config port B, bus 3 dev 8 func 0, tag PCIX BRIDGE
2012-07-23 17:55:59.860 0:0:0>End  : IO-Bridge unit 1 Config MB bridges
2012-07-23 17:55:59.889 0:0:0>Begin: IO-Bridge unit 1 PCI id test 
2012-07-23 17:56:00.191 0:0:0>  INFO:100000 count read passed for MB/IOB_PCIEb/BRIDGE! Last read VID:1166|DID:103
2012-07-23 17:56:00.511 0:0:0>  INFO:100000 count read passed for MB/IOB_PCIEb/BRIDGE_GBE! Last read VID:14e4|DID:1668
2012-07-23 17:56:00.838 0:0:0>  INFO:100000 count read passed for MB/IOB_PCIEb/BRIDGE_GBE! Last read VID:14e4|DID:1668
2012-07-23 17:56:01.159 0:0:0>  INFO:100000 count read passed for MB/IOB_PCIEb/BRIDGE_PCIX! Last read VID:1166|DID:104
2012-07-23 17:56:01.543 0:0:0>  INFO:100000 count read passed for MB/IOB_PCIEb/BRIDGE/GBE! Last read VID:14e4|DID:1648
2012-07-23 17:56:01.927 0:0:0>  INFO:100000 count read passed for MB/IOB_PCIEb/BRIDGE/GBE! Last read VID:14e4|DID:1648
2012-07-23 17:56:02.306 0:0:0>  INFO:100000 count read passed for MB/IOB_PCIEb/BRIDGE/HBA! Last read VID:1000|DID:50
2012-07-23 17:56:02.354 0:0:0>End  : IO-Bridge unit 1 PCI id test 
2012-07-23 17:56:02.370 0:0:0>Begin: Quick JBI Loopback Block Mem Test
2012-07-23 17:56:02.396 0:0:0>Quick jbus loopback Test 262144 bytes at 00000000.00a50000
2012-07-23 17:56:04.963 0:0:0>End  : Quick JBI Loopback Block Mem Test
2012-07-23 17:56:04.984 0:0:0>INFO:
2012-07-23 17:56:04.992 0:0:0>  POST Passed all devices.
2012-07-23 17:56:05.007 0:0:0>POST:     Return to VBSC.
2012-07-23 17:56:05.029 0:0:0>Master set ACK for vbsc runpost command and spin...